system verilog - Making connections to SV generated interfaces -

i need make connections ports of systemverilog interface have been generated. don't know instance names of generated interfaces are, can't work out how connect them.

e.g., if generate code this:

generate   (genvar abc_if_inst = 0; abc_if_inst < num_abc; abc_if_inst++)     abc_if   if_abc   (.clk(clk), .resetn(resetn)); endgenerate 

how reference interface signals, e.g. i'm assuming it's this:

.port_x (if_abc_gen_inst_num.port_x), .port_y (if_abc_gen_inst_num.port_y), 

it best put begin-end around content of for-loop , apply label. if not use label automatic label added genblk suffixed unique id number. section 27.6 of ieee std 1800-2012 goes detail explain generate block naming works. section 27 generate blocks. 1 example generate for-loops on page 753.

for provided code, try:

generate   (genvar abc_if_inst=0; abc_if_inst<num_abc; abc_if_inst++) begin : mygen     abc_if   if_abc   (.clk(clk), .resetn(resetn));   end endgenerate 

then can connect as:

.port_x (mygen[0].if_abc.port_x), .port_y (mygen[0].if_abc.port_y), // ... .port_x (mygen[num_abc-1].if_abc.port_x), .port_y (mygen[num_abc-1].if_abc.port_y), 

note index of mygen needs constant, such parameter, genvar, or hard coded value.